Field of the Invention
The invention relates to a memory configuration having a connection area and cell arrays that adjoin the connection area. The cell array has a matrix-like memory with row and column decoders that are each connected to address lines.
Semiconductor memories are typically built up from small, regular cell units (e.g., in the case of a 256 Mb DRAM, the cell units are 4 Mb). The cell units are combined into larger configurations (cell arrays) that, in the case of a 256 Mb DRAM, in turn often have a size of 64 Mb. In the case of the 256 Mb DRAM, it is, therefore, necessary for four of these cell arrays to be disposed on the module. It is often the case that two cell arrays are disposed beside each other in each case and a connection area is formed between two adjacently disposed cell arrays. The connection area has bonding pads that are connected to the switching elements of the cell arrays and are used for connecting further circuits. Because an individual cell array often has a side ratio of 2:1, and the connection area is relatively small, the result, for example, in the case of the 256 Mb DRAM having four cell arrays, is immediately an overall side ratio of 2:1. In the case of a 512 Mb DRAM, in which eight cell arrays (512 M=8*64 M) then have to be placed, two alternatives then remain in the prior art:
a) four cell arrays beside one another; or
b) in each case four cell arrays in a 2*2 configuration on both sides of the connection area.
Both configurations have an unfavorable side ratio of 4:1 (case(a)) or 1:1 (case(b)). Under certain circumstances, the side ratios lead to chip dimensions that no longer fit into standardized housings.
It is accordingly an object of the invention to provide a memory configuration with a central connection area that overcomes the herein afore-mentioned disadvantages of the heretofore-known devices of this general type and that provides memory arrays with a more flexible construction.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a memory configuration including address lines, cell arrays having side edges, and a centrally disposed connection area having four side edges, including longitudinal sides, and connecting pads. The cell arrays adjoin the connection area, are disposed on each of the four side edges of the connection area in a closed ring around the connection area, each have a matrix-like memory with decoders each connected to at least one of the address lines, each have at least two side edges adjoining side edges of two other ones of the cell arrays, and each are subdivided in a longitudinal direction into a first cell subarray and a second cell subarray. The connecting pads are electrically connected to the cell arrays. Each of the first and second cell subarrays have longitudinal sides adjoining the connection area and another one of the cell arrays and a decoder disposed at right angles to one of the longitudinal sides adjoining one of the group consisting of the connection area and the another one of the cell arrays. Each of the cell arrays having two mutually adjoining decoders is disposed in a center of one of the longitudinal sides of the connection area. A first of the decoders is connected to first of the address lines disposed parallel to the longitudinal direction in the first cell subarray. A second of the decoders connected to second of the address lines disposed parallel to the longitudinal direction in the second cell subarray.
A significant advantage of the invention is that a centrally disposed connection area is provided, which is surrounded annularly by cell arrays. As such, a very compact configuration of a large number of cell arrays in one memory configuration is achieved.
In accordance with another feature of the invention, the decoders of each of the cell arrays include row decoders and column decoders each connected to the address lines.
In accordance with a further feature of the invention, the decoder of each of the first and second cell subarrays is one of the group consisting of a row decoder and a column decoder.
In accordance with an added feature of the invention, the connection area is rectangular and has four corner areas, the cell arrays are each rectangular, each of the four side edges of the connection area have a respective length, four of the cell arrays adjoin a respective one of the four side edges of the connection area and each of the four cell arrays have a side edge with a length equal to the respective length of each of the four side edges, others of the cell arrays are respectively disposed in each of the four corner areas, and an overall area defined by the connection area and the cell arrays is rectangular.
In addition, it is advantageous to construct the connection area and the cell arrays rectangularly, a cell array with a side edge of an appropriate size adjoining each side edge of the connection area. In each case, a further cell array is disposed in the corner areas of the connection area. Such a memory configuration embodiment has a rectangular outer contour. Therefore, the memory configuration is particularly suitable for a standard housing having a side edge ratio of 2:1.
In accordance with an additional feature of the invention, a line decoder or a row decoder is constructed in the areas of the side edges of a cell array that adjoins another cell array or the connection area. As such, the line or row decoder is disposed relatively close to the central connection area so that the signal paths for reading data out or writing data into the cell arrays are relatively short.
In accordance with yet another feature of the invention, the connection area has transverse sides, the connecting pads include connecting pad rows, a first row, a second row, a third row, and a fourth row of the connecting pad rows are disposed at a predefined distance parallel to the transverse sides of the connection area, a fifth row and a sixth row of the connecting pad rows are disposed at a predefined distance parallel to the longitudinal sides of the connection area, the first and second rows and the third and fourth rows are respectively disposed on a given line and are disposed at a predefined distance from one another, and the fifth row and the sixth row are respectively disposed centrally with respect to the first and third rows and the second and fourth rows.
In accordance with yet a further feature of the invention, the fifth row and the sixth row are respectively disposed between the first, second, third, and fourth rows.
In accordance with yet an added feature of the invention, the is fifth row and the sixth row are respectively disposed between the first and third rows and the second and fourth rows and the longitudinal edges of the connection area.
In a preferred embodiment, the bonding pads in the connection area are disposed in the form of four rows, the four rows being disposed parallel to the four outer edges of the connection area. As such, a symmetrical distribution of the connecting pads is made possible.
In accordance with yet an additional feature of the invention, there are provided peripheral circuits for operating the cell arrays, the peripheral circuits connected to the cell arrays and disposed in the connection area.
It is advantageous to configure peripheral circuits in the central connection area. The peripheral circuits are, therefore, virtually equally far removed from all the cell arrays, so that propagation time differences between the signals from various cell arrays are relatively small.
In accordance with again another feature of the invention, a cell array preferably has approximately the same size as the connection area.
In accordance with again a further feature of the invention, each cell array is once more divided into two cell subarrays.
In accordance with a concomitant feature of the invention, the connection area and/or the cell arrays are twice as long as they are wide.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory configuration with a central connection area, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may he made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.